1. Field of the Invention
This invention relates to a counter device for counting clock pulses and to a method of driving the counter device. More particularly, the invention relates to an asynchronous binary counter and a method of operating the same, and a memory device with the counter embedded therein and operating method thereof.
2. Description of the Background Art
Counter devices are used in various fields. Certain types of counter devices are used as timers, with a count thereof corresponding to a period of time, to generate a control signal for actuating or stopping a particular component at every predetermined counts.
In a certain system, a plurality of components are affixed with numbers, and a counter device is used for successively actuating the components according to the numbering. In this construction, a component of a number corresponding to a count of the counter device is actuated.
In a serially accessible memory device, word lines (rows) or bit lines (columns) are successively selected. A counter device called a program counter (or an address counter) is used to generate an address for designating a word line or a bit line to be selected. In this construction, the counter device successively increments or decrements its count in response to a control signal, and the count is used as an address for designating a word line or a bit line.
FIG. 1 is a view showing one example of conventional asynchronous binary counters, which is exemplified in "Principle of CMOS VLSI Design--A Systems Perspective" by Nell Weste et al, FIG. 8.25 on pages 335-336, published 1985, by Addison-Wesley Publishing Company.
Referring to FIG. 1, a conventional asynchronous binary counter 7 is a one-bit counter including a first-stage latch block 71 and a second-stage latch block 72. The first-stage latch block 71 includes transmission gates 6a and 6b which turn on and off in response to two phase non-overlapping, or complementary clock signals .phi., .phi. applied through inputs C, C, and inverters 8a and 8b for inverting signals applied thereto. In response to the clock signals .phi., .phi., the transmission gate 6a passes an output Q generated from the second-stage latch block 72. The transmission gate 6b, in response to the clock signals .phi., .phi., connects an input of the inverter 8a and an output of the inverter 8b. The inverter 8a inverts a signal received from the transmission gate 6a. The inverter 8b inverts a signal received from the inverter 8a.
Generally, a transmission gate has a construction in which the sources and the drains of an n-channel MOS (insulated gate field effect) transistor and a p-type MOS transistor are interconnected. The clock signals applied to control terminals of the transmission gates 6a and 6b have different phases, so that the transmission gates 6a and 6b turn on and off in a complementary manner.
Similarly, the second-stage latch block 72 includes transmission gates 6c and 6d, and two inverters 8a and 8b connected in series. The inverter 8c outputs the signal Q, and the inverter 8d outputs a signal Q. The transmission gate 6c operates synchronously with the transmission gate 6b, while the transmission gate 6d with the transmission gate 6a.
The latch block 71 is in a through state when the clock signal .phi. is "H" , and in a latching state when the clock signal .phi. is "L". The latch block 72 is in a through state when the clock signal .phi. is "L", and in a latching state when the clock signal .phi. is "H". The latching state is a state for continuously outputting an immediately preceding input signal regardless of a current input signal, whereas the through state is a state for just passing an input signal therethrough as an output.
The binary counter shown in FIG. 1 is a one-bit counter, and in practical use, normally, a plurality of such one-bit binary counters 7 are connected in series as shown in FIG. 2. FIG. 2 shows a construction for implementing an n+1-bit binary counter with n+1 one-bit binary counters 7a-7n connected in series.
In the asynchronous counter shown in FIG. 2, input signals (count inputs, i.e. clock signals .phi., .phi.) are applied only to the counter of the least significant bit. Each of the remaining counters receives outputs Q, Q of a counter of the lower bit at count inputs C, C. More particularly, referring to FIG. 1, a higher bit counter receives outputs Q, Q of a lower bit counter instead of the clock signals .phi., .phi.. In such a counter, each counter excluding a first stage receives an output of a preceding counter stage as a clock signal. Clock signals to be count are applied only to the first counter stage. Such a counter is called an asynchronous counter or a ripple counter. An operation will be .described next with reference to FIG. 3. FIG. 3 is a diagram showing operational waveforms of 3-bit binary counters 7a-7c (FIG. 2), i.e. three of the counter in FIG. 1 connected in a 3-stage series.
It is assumed that, in an initial state prior to application of the clock signals .phi., .phi., counter outputs Q0, Q1 and Q2 are all maintained in "L" level (logical "0").
The counter 7a at the first stage operates as follows. When the clock signal .phi. rises to "H" (logical "1"), the transmission gate 6a turns on to transmit an signal (output Q) to the first-stage latch block 71. The transmission gates 6b and 6c remain in an off state.
When the clock signal .phi. falls from "H" to "L", the transmission gate 6a turns off and the transmission gate 6b on, thereby establishing data "L" in the first-stage latch block 71 owing to its latching function. Simultaneously, the established data "L" is transmitted from the first-stage latch block 71 to the second-stage latch block 72 through the transmission gate 6c. As a result, output Q0 of the first-stage counter 7 becomes "H", and output Q0 is "L".
When the clock signal .phi. rises to "H" again, the transmission gate 6c in the second-stage latch block 72 turns off, and the transmission gate 6d turns on, thereby establishing data in the second-stage latch block 72, i.e. output data Q0 and Q0. The established output data Q0 in "H" level is transmitted to the first-stage latch block 71, and through the transmission gate 6a in the ON state to the inverter 8a.
When the clock signal .phi. falls from "H" to "L" again, the transmission gate 6b in the ON state forms a latch circuit in the first-stage latch block 71, thereby establishing data "H" in the first-stage latch block 71. Simultaneously, this data "H" is transmitted through the transmission gate 6c in the ON state to the inverter 8c in the second-stage latch block 72. As a result, output Q0 becomes "L" and output Q0 "H".
By repeating this operation, the state of output Q0 of the first counter 7a changes each time the clock signal .phi. falls from "H" to "L". Output Q0 falls from "H" to "L" at every second fall of the clock signal .phi.. Thus, a one-bit counter having counts "0" and "1" is realized.
The counter 7b at the second stage receives outputs Q0, Q0 of the first counter 7a at the count inputs C, C. Consequently, the second counter 7b is operable by using output Q0 as its clock signal instead of the clock signal .phi. used in the first counter 7a. Thus, the state of output Q1 of the second counter 7b changes each time the output Q0 of the first counter 7a falls from "H" to "L". That is, output Q1 falls from "H" to "L" at every second fall of output Q0 of the first counter 7a and, therefore, returns to an initial state at every four counts of the clock signal .phi..
The counter 7c at the third stage receives outputs Q1, Q1 of the second counter 7b as count inputs. Thus, the state of output Q2 of the third counter 7c changes each time the output Q1 of the second counter 7b falls from "H" to "L". The third counter 7c operates in a period twice that of the second counter 7b and, therefore, returns to an initial state at every eight counts of the clock signal .phi..
Where, as described above, three counters 7a-7c are connected in series, a binary counter for counting up clock signals .phi. and providing counts in binary notation is realized by using output Q2 as the most significant bit and output Q0 as the least significant bit.
Similarly, a count-down binary counter is obtained by using outputs Q of respective counter stages.
The conventional binary counter is constructed as described above, which receives clock pulses as count inputs and provides counts in binary notation. Since this binary counter continuously outputs counts, such counter may be used in the field of sequence control, for example, in which a plurality of components are successively actuated according to the above counts.
However, the conventional counter has a limited application since its output is successively incremented or decremented one by one, the counter being unable to jump certain predetermined counts.
Assume, for example, that counts 0-5 (decimal numbers) of the counter are used as signals to determine timing for actuating components of system A, counts 6-10 (decimal numbers) for actuating components of system B and counts 1-15 (decimal numbers) for actuating components of system C. Each component is in one-to-one relationship with a count of the counter.
Where the components of systems A, B and C are actuated successively, sequence control may be effected by using the counter. However, the conventional counter cannot be used as a timing generator or a component selecting signal generator for a control system which successively actuates the components of systems A, B and C under certain conditions but successively actuates only those of systems A and C under others.
To cope with such a situation, possible consideration is to provide counters for the respective systems A, B and C and switch from one counter to another. However, this would require a control device for the switching, resulting in a large and complicated counter device. Even if such devices were used, components to be maintained inactive would be determined in a fixed manner by a timer, which makes it impossible to obtain a flexible control system configuration allowing variable the components to be maintained inactive.
A serially accessible memory such as a field or frame memory is used in the field of image processing. In such a memory, a counter device such as a program counter is used as an address generator to generate a row or column designating signal for selecting a word line or a bit line. The following problem arises in such a memory. Assume a screen split up into three image areas A, B and C. The screen may be split up vertically or horizontally, and here it is assumed that the screen is split up vertically into three parts as shown in FIG. 4. In the case of a field memory or a plane memory in FIG. 4, the word lines WL correspond to horizontal scan lines on the screen, and are successively selected in accordance with counter outputs.
In a field memory of FIG. 4, pixels on the screen are generally corresponding in one-to-one mapping relation to the bits (memory cells) in a memory cell array 950. A counter/decoder 951 selects a word line WL from a memory cell array 950 in response to a clock signal .phi.c. In other words, the counts of the counter are used as row addresses. If, in the course of image editing, it is desired to process data by reading the data for the image areas A and C only, omitting the image area B, it is necessary to apply word line designating signals from outside since the conventional counter cannot be used as an address generator in such a case, which makes a high-speed word line selection impossible. More specifically, the counter/driver 951 can not jump from a word line WLa of the last word line in the area A to a word line WLb of the first word line in the area C in one clock cycle.
If the counter/decoder 951 is employed to jump the area A (word line WLa) to the area C (word line WLb), it is required to disable the data read/write operation of the memory device while the clock signal .phi.c is applied to the counter/decoder successively by a certain number of times to set an output of the counter/decoder corresponding to the word line WLb. This scheme degrades data processing performance.
When, during a data writing operation, it is desired to update the data for the image areas A and C, leaving the data for the image area B unchanged, the same problem arises since the conventional counter cannot be used as a row address generator. Also where the screen is split up horizontally, the same problem arises if a counter is used for generating bit line selecting addresses.
In the absence of the count jumping function, i.e. a function to jump from one count to another, as described above, the conventional counter has the disadvantage of having a limited application in that it cannot be used for applications requiring such count jumping actions.
As described above, where an address counter only operates in response to a clock signal and it is not provided with a jumping function, a memory device with such an address counter may only employable as a buffer memory.
In image data processor, such a buffer memory is frequently employed. A typical use of such a buffer memory on an image data processor is shown in FIG. 5.
FIG. 5 is a block diagram of an interframe comparison type comb filter. Referring to FIG. 5, a frame buffer 910 receives a composite video signal, and delays received composite video signal by one frame period. The frame buffer 910 is a first-in, first-out memory, and serves as a one frame delay element.
An adder 911 receives current composite video signal at its positive input and an output of the frame buffer 910 at its negative input. The adder 911 serves as a subtractor for subtracting, from current video signal, video signal preceding by one frame period to the current video signal.
An amplifier 912 has an amplification rate of 1/2 and serves as a divider by a factor of 2.
A bandpass filter 913 passes only a desired frequency components from received signal from the amplifier 912. The bandpass filter 913 has a pass band of 3.58 MHz and produce a chrominance signal C.
An adder 914 receives an output of the bandpass filter 913 at its negative input and the current video data at its positive input. The adder 914 serves as a subtractor for subtracting the output of the bandpass filter 913 or a chrominance signal from current composite video signal to produce a luminance signal.
FIG. 6 shows schematically an overall structure of a FIFO type memory device. The memory device can perform asynchronously data read operation and data write operation.
Referring to FIG. 6, the FIFO type memory device includes a memory cell array 801 having a plurality of memory cells arranged in rows and columns, and a row decoder 802 for decoding a row address received from a selection control unit 804 to select a corresponding row in the memory cell array 801. The selection control circuit 804 passes either of outputs of a read row address counter 806 and a write row address counter 808.
The read row address counter 806 increments its count by 1 in response to a first read clock signal .phi.R1 from a read-out clock generator 810. The read-out clock generator 810 generates the first clock .phi.R1 and a second read clock signal .phi.R2 in response to externally applied read enable signal RE and read control signal .phi.R.
The read-out clock generator 810 gates the read clock signal .phi.R to generate the second read clock signal .phi.R2, and also generates the first read clock signal .phi.R1 when the read clock .phi.R is applied thereto by the times of the number of columns of the array 801.
The write row address counter 808 increments its count by 1 in response to the reception of a first write clock signal .phi.W1 from a write-in clock generator 812 which in turn generates the first write clock signal .phi.W1 and a second write clock signal .phi.W2 in response to externally applied write enable signal WE and write control signal .phi.W.
The second write clock signal .phi.W2 is generated by gating the write clock signal .phi.W by the write enable signal WE. The first write clock signal .phi.W1 is generated when the second write control signal .phi.W2 is generated by the times of the number of the columns in the array 801.
The memory device of FIG. 6 also includes a serial read counter 814 for generating a column select signal in response to the second read clock signal .phi.R2, a read-out buffer 816 for storing data of one row of the array 801, and an output buffer 818 for receiving data from the read-out buffer 816 to produce an external read-out data Dout. The serial read counter 814 includes a read column address counter 834 for counting the second read clock signal .phi.R2 to generate a read column address, and a read decoder 832 for decoding a read column address from the read column address counter 834 to generate a column select signal.
The read-out buffer 816 includes a plurality of storage elements corresponding in number and position to the columns of the array 801 and connects sequentially the storage elements to the output buffer 818 in response to the column select signal from the read decoder 832.
The memory device further includes a serial write counter 820 for generating a write column select signal in response to the second write clock signal .phi.W2, and a write-in buffer 822 for storing write-in data of one row to the array 801 received from an input buffer 824. The input buffer 824 produces write-in data from externally applied write-in data. The write-in buffer 822 includes a plurality of storage elements corresponding in number and position to the columns of the array 801. The write-in buffer 822 connects sequentially the storage elements therein to the input buffer 824 in response to the column select signal received from the serial write-in counter 820.
The serial write-in counter 820 includes a write column address counter 838 for counting the second write-in clock signal .phi.W2 to generate a write column address, and a write decoder 836 for decoding a write column address from the write column address counter 838 to generate a write column select signal.
The selection control circuit 804 arbitrates between a read row selection and a write row selection, controls sensing operation in the array 801, and also controls the data transfer between the array 801 and the read-out buffer 816 and between the array 801 and the write-in buffer 822. Now operation of the memory device will be briefly described.
In data writing operation, the write enable signal WE is brought into an active state. The write-in clock generator 812 is made active in response to the activated write enable signal WE to generate the first and second write clock signals .phi.W1 and .phi.W2. The write column address counter 838 counts the second write clock signal .phi.W2, and supplies its count to the write decoder 836 as a write column address. A storage element in the write-in buffer 822 selected by the write decoder 836, or designated by a write column address from the decoder 836, is connected to the input buffer 824 to receive and store write-in data.
The write-in clock generator 812 generates the first write clock signal .phi.W1 at an appropriate timing in response to the write clock .phi.W. The write-row address counter 808 generates a write row address in response to the first write control signal .phi.W1. The selection control unit 804 detects the transition of the output of the write-row address counter 808 to pass the write row address from the counter 808 to the row decoder 802. The row decoder 802 selects in the array 801 a row corresponding to the received row address. When the write-in buffer 122 receives and stores one row amount of data, the selection control unit 804 connects the write-in buffer 822 and the array 801, so that data in the write-in buffer 822 are transferred in parallel to memory cells on the selected row in the array 801.
In data reading operation, the read enable signal RE is brought into an active state to activate the read-out clock generator 810. The first read clock signal .phi.R1 is generated from the read-out clock generator 810 to be applied to the read-row address counter 806. The read-row address counter 806 increments its count by 1 every receipt of the first read clock signal .phi.R1. When the selection control unit 804 detects the transition of the count of the counter 806, it passes through the output or the count of the read-row address counter 806 to provide the same to the row decoder 802 as a read row address. The row decoder 802 selects a row corresponding to thus received row address from the counter 806 in the array 801.
After selection of the row and assertion of data potential on each column, the array 801 is connected to the read-out buffer 816 under the control of the selection control unit 804, so that data of a selected row in the array 801 are transferred from the array 801 to the read-out buffer 816.
Then, the read-out clock generator 810 generates the second read clock signal .phi.R2 to provide the same to the read column address counter 834. The read column address counter 834 increments its count by 1 every receipt of the second read clock signal .phi.R2, and provides its count to the read decoder 832 as a read column address. The read decoder 832 connects sequentially the storage elements of the read-out buffer 816 to the output buffer 818 in response to received read column addresses.
When the read enable signal RE and the write enable signal WE are both active, the selection control unit 804 arbitrates between read row selecting operation and write row selecting operation. In general, read row selecting operation is first performed and then write row selecting operation is performed in one clock cycle if the clock signals .phi.R1 and .phi.W1 are synchronized with each other. If the clock signals .phi.R1 and .phi.W1 are asynchronous with each other, the selection control unit 804 selects first a row address generated earlier. The selection control unit 804 also monitors a read row address and a write row address to prevent the read row address from being in advance of the write row address.
With such a FIFO type memory device, video data of raster scan system can be processed at a fast rate. When the read clock .phi.R and the write clock .phi.W are synchronous with each other, the memory device serves as a delay element such as a field delay element or a frame delay element.
In such a memory device used in video application, data sequence in data reading operation should be made the same as that in data writing operation. Thus, a conventional redundancy scheme cannot be employed for repairing a defective memory cell (a defective bit).
FIG. 7 shows a structure of a memory device with a conventional redundancy scheme. In FIG. 7, only circuitry related to defective row repairing is shown. Referring to FIG. 7, a row decoder RD and a spare row decoder correspond to the row decoder 802 shown in FIG. 6, and a row address counter RAD corresponds to the read-row address counter 806 or the write-row address counter 808 shogun in FIG. 6. The memory cell array 801 of FIG. 6 includes a memory cell array MA and a redundant array MR of FIG. 7. The redundant array MR includes one or more redundant word lines for repairing a defective word line having a defective memory cell in the memory cell array MA.
The spare row decoder SRD stores a defective row address indicating a defective row in the memory cell array MA. The programing of the defective row address is performed by blowing off one or more fuse elements provided in the spare row decoder SRD with a laser beam, for example.
The output of the row address counter RAD is supplied both to the row decoder RD and to the spare row decoder SRD. When a row address from the counter RAD designates a normal row in the array MA, the row decoder RD decodes the received row address to select a corresponding row in the array MA. The spare row decoder SRD does not generate an active signal (redundant row selecting signal), and no redundant word line is selected in the redundant array MR.
If a row address from the row address counter RAD designates the defective row in the memory cell array MA, the spare row decoder SRD generates a redundant row selecting signal to select a corresponding redundant row in the redundant array MR because the row address from the row address counter RAD coincides with the stored defective row address in the spare row decoder SRD. The spare row decoder SRD also generates a normal element disable signal NED to deactivate the row decoder RD for inhibiting row selection in the memory cell array MA. In other words, the row decoder RD performs decoding operation according to the received row address until the normal element disable signal NED is generated.
According to the redundancy scheme, a defective row (word line) WLD is replaced with a redundant row WLR as shown in FIG. 8(a), so that the defective word line WLD is equivalently repaired.
However, in the shown redundancy scheme, the row decoder RD is once activated, and then it is deactivated in response to the normal element disable signal NED. Thus, there is a time period in which the defective row is activated in the memory cell array MA to connect the memory cells thereon to respective columns. In order to avoid data contention on the columns between data of the defective row and data of the redundant row, it is necessary to wait for the activation of the redundant row until the defective row is deactivated, resulting in increased access time.
In addition, the mapping of video data in the memory cell array MA is in general the same as that on a display screen CRT as shown in FIG. 8. With the above described redundancy scheme, such a correspondence in mapping can not be maintained.
For a certain application, such destruction in mapping correspondence may not be a problem as far as a row word line selection is concerned because it can not be seen from an outer world how row addresses are made correspondent to physical dispositions of rows in a memory cell array.
However, in a video application video data are serially input and output to and from a memory, and the sequence of video data is required to be the same in input data and output data. Therefore, the above described redundancy scheme can not be applied to the very column repairing scheme.
Possible scheme for accommodating such a difficulty in column repairing may be that as shown in FIG. 9. In FIG. 7 a defective column line CLD having connected thereto defective memory cell is indicated by the mark "x" is replaced with a redundant column CLR. A storage element a2 is connected through a transfer gate transistor TG2 to the redundant column CLR. With the repairing scheme, the sequence of video data a1 to an is maintained in data inputting and in data outputting.
However, in the scheme, the redundant column CLR is connected through a long interconnection line IL to the transfer gate transistor TG2, and it takes longer time for data transfer between the storage element a2 and the redundant column CLR as compared to any other normal column-to- storage element data transfer, deteriorating fast operability.
In order to connect the redundant column CLR to the transistor TG2, fuse elements may be employed, and fuse elements between the transfer gate transistors for normal columns and the interconnection line IL may be blown off with a laser beam, as has been done in programming a ROM. However, it is difficult in practice to execute correctly such a repairing interconnection technique because there are many fuse elements to be blown off, leading to reduction in product yield.